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1 features ? 20ns maximum (5 volt su pply) address access time ? asynchronous operation for compatibility with industry- standard 512k x 8 srams ? ttl compatible inputs and output levels, three-state bidirectional data bus ? operational environment: - total dose: 50 krads(si) - sel immune 110 mev-cm 2 /mg - seu let th (0.25) = 52 cm 2 mev - saturated cross section 2.8e-8 cm 2 /bit -< 1.1e-9 errors/bit-day, adams 90% worst case environment geosynchronous orbit ? packaging: - 36-lead ceramic fl atpack (3.831 grams) ? standard microcircuit drawing 5962-00536 - qml q and v compliant part introduction the UT9Q512E radtol product is a high-performance cmos static ram organized as 524,288 words by 8 bits. easy memory expansion is provided by an active low chip enable (e ), an active low output enable (g ), and three-state drivers. writing to the device is accompli shed by taking chip enable (e ) input low and write enable (w ) inputs low. data on the eight i/o pins (dq 0 through dq 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). reading from the device is accomplished by taking chip enable (e ) and output enable (g ) low while forcing write enable (w ) high. under these conditions, the cont ents of the memory location specified by the address pins wi ll appear on the i/o pins. the eight input/output pins (dq 0 through dq 7 ) are placed in a high impedance state when th e device is deselected (e high), the outputs are disabled (g high), or during a write operation (e low and w low). standard products UT9Q512E 512k x 8 radtol sram data sheet september, 2008 memory array 1024 rows 512x8 columns pre-charge circuit clk. gen. row select a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 i/o circuit column select data control clk gen. a10 a11 a12 a13 a14 a15 a16 a17 a18 dq 0 - dq 7 w g e figure 1. UT9Q512E sram block diagram
2 pin names device operation the UT9Q512E has three control inputs called chip enable (e ), write enable (w ), and output enable (g ); 19 address inputs, a(18:0); and eight bidirectional data lines, dq(7:0). e controls device selection, active, and standby modes. asserting e enables the device, causes i dd to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. w controls read and write oper ations. during a read cycle, g must be asserted to enable the outputs. table 1. device operation truth table notes: 1. ?x? is defined as a ?don?t care? condition. 2. device active; outputs disabled. read cycle a combination of w greater than v ih (min) and e less than v il (max) defines a read cycle. r ead access time is measured from the latter of chip enable, output enable, or valid address to valid data output. sram read cycle 1, the address access in figure 4a, is initiated by a change in address inputs while the chip is enabled with g asserted and w deasserted. valid data appears on data outputs dq(7:0) after the specified t av q v is satisfied. outputs remain active throughout the entire cycle. as long as chip enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (t avav ). sram read cycle 2, the chip enable - controlled access in figure 4b, is initiated by e going active while g remains asserted, w remains deasserted, and the addresses remain stable for the entire cycle. after the specified t etqv is satisfied, the eight-bit word addressed by a(18:0) is accessed and appears at the data outputs dq(7:0). sram read cycle 3, the output enable - controlled access in figure 4c, is initiated by g going active while e is asserted, w is deasserted, and the addresse s are stable. read access time is t glqv unless t avqv or t etqv have not been satisfied. a(18:0) address dq(7:0) data input/output e chip enable w write enable g output enable v dd power v ss ground 136 235 334 433 532 631 730 829 928 10 27 11 26 12 25 13 24 14 23 15 22 16 21 17 20 18 19 figure 2. UT9Q512E 20ns sram pinout (36) nc a18 a17 a16 a15 g dq7 dq6 v ss v dd dq5 dq4 a14 a13 a12 a11 a10 nc a0 a1 a2 a3 a4 e dq0 dq1 v dd v ss dq2 dq3 w a5 a6 a7 a8 a9 g w e i/o mode mode x 1 x 1 3-state standby x 0 0 data in write 1 1 0 3-state read 2 0 1 0 data out read
3 write cycle a combination of w less than v il (max) and e less than v il (max) defines a write cycle. the state of g is a ?don?t care? for a write cycle. the outputs are placed in the high-impedance state when either g is greater than v ih (min), or when w is less than v il (max). write cycle 1, the write enable - controlled access in figure 5a, is defined by a write terminated by w going high, with e still active. the write pulse width is defined by t wlwh when the write is initiated by w , and by t etwh when the write is initiated by e . unless the outputs have been previously placed in the high- impedance state by g , the user must wait t wlqz before applying data to the nine bidirectional pins dq(7:0) to avoid bus contention. write cycle 2, the chip enable - controlled access in figure 5b, is defined by a write terminated by e going inactive. the write pulse width is defined by t wlef when the write is initiated by w , and by t etef when the write is initiated by the e going active. for the w initiated write, unless the outputs have been previously placed in the high-impedance state by g , the user must wait t wlqz before applying data to the eight bidirectional pins dq(7:0) to avoid bus contention. operational environment table 2. operation al environment design specifications 1 notes: 1. the sram will not latchup during radiation exposure under recommended operating conditions. 2. adam?s 0% worst case environment, geosynchronous orbit, 100 mils of aluminum. to tal d ose 50 krad(si) heavy ion error rate 2 < 1.1e-9 errors/bit-day
4 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may caus e permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. exposure to absolute maximum rating conditions for extended periods may aff ect device reliability and performance. 2. maximum junction temperat ure may be increased to +175 c during burn-in an d steady-static life. 3. test per mil-std-883, method 1012. recommended operating conditions symbol parameter limits v dd dc supply voltage -0.5 to 7.0v v i/o voltage on any pin -0.5 to 7.0v t stg storage temperature -65 to +150 c p d maximum power dissipation 1.0w t j maximum junction temperature 2 +150 c jc thermal resistance, junction-to-case 3 10 c/w i i dc input current 10 ma symbol parameter limits v dd positive supply voltage 4.5 to 5.5v t c case temperature range (c) screening: -55 c to +125 c (w) screening: -40 c to +125 c v in dc input voltage 0v to v dd
5 dc electrical characteristics (pre/post-radiation)* -55 c to +125 c for (c) screening and -40 o c to +125 o c for (w) screening (v dd = 5.0v + 10%) notes: * post-radiation perform ance guaranteed at 25 c per mil-std-883 method 1019. 1. measured only for in itial qualification and after process or design ch anges that could affect input/output capacitance. 2. supplied as a design limit bu t not guaranteed or tested. 3. not more than one output may be shorted at a time for maximum duration of one second. 4. g = v 1h symbol parameter condition min max unit v ih high-level input voltage (ttl) 2 v v il low-level input voltage (ttl) 0.8 v v ol1 low-level output voltage i ol = 8ma, v dd =4.5v (ttl) 0.4 v v ol2 low-level output voltage i ol = 200 a,v dd =4.5v (cmos) 0.05 v v oh1 high-level output voltage i oh = -4ma,v dd =4.5v (ttl) 2.4 v v oh2 high-level output voltage i oh = -200 a,v dd =4.5v (cmos) 3.2 v c in 1 input capacitance ? = 1mhz @ 0v 10 pf c io 1 bidirectional i/o capacitance ? = 1mhz @ 0v 12 pf i in input leakage current v in = v dd and v ss, v dd = v dd (max) -2 2 a i oz three-state output leakage current v o = v dd and v ss v dd = v dd (max) g = v dd (max) -2 2 a i os 2, 3 short-circuit output current v dd = v dd (max), v o = v dd v dd = v dd (max), v o = 0v -90 90 ma i dd (op) 4 supply current operating @ 1mhz inputs: v il = 0.8v, v ih = 2.0v i out = 0ma v dd = v dd (max) 50 ma i dd (op) 4 supply current operating @50mhz inputs: v il = 0.8v, v ih = 2.0v i out = 0ma v dd = v dd (max) 76 ma i dd (sb) supply current standby @0mhz inputs: v il = v ss i out = 0ma e = v dd - 0.5 v dd = v dd (max) v ih = v dd - 0.5v 10 45 ma ma -55 c, -40 c, 25 c 125 c
6 { { } } v load + 500mv v load - 500mv v load v h - 500mv v l + 500mv active to high z levels high z to active levels figure 3. 5-volt sram loading ac characteristics read cycle (pre/post-radiation)* -55 c to +125 c for (c) screening and -40 o c to +125 o c for (w) screening (v dd = 5.0v + 10%) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. functional test. 2. three-state is defined as a 500mv change fr om steady-state output voltage (see figure 3). 3. the et (chip enable true) notatio n refers to the falling edge of e . seu immunity does not af fect the read parameters. 4. the ef (chip enable false) notation refers to the rising edge of e . seu immunity does not aff ect the read parameters. symbol parameter min max unit t avav 1 read cycle time 20 ns t av q v read access time 20 ns t axqx output hold time 3 ns t glqx g -controlled output enable time 0 ns t glqv g -controlled output enable time (read cycle 3) 10 ns t ghqz 2 g -controlled output three-state time 10 ns t etqx 3 e -controlled output enable time 3 ns t etqv 3 e -controlled access time 20 ns t efqz 1,2,4 e -controlled output three-state time 10 ns
7 assumptions: 1. e and g < v il (max) and w > v ih (min) a(18:0) dq(7:0) figure 4a. sram read cycle 1: address access t avav t avqv t axqx previous valid data valid data assumptions: 1. g < v il (max) and w > v ih (min) a(18:0) fi 4bsramrdcl2chie blc llda e data valid t efqz t etqv t etqx dq(7:0) figure 4b. sram read cycle 2: chip enable-controlled access figure 4c. sram read cycle 3: output enable-controlled access a(18:0) dq(7:0) g t ghqz assumptions: 1. e < v il (max) and w > v ih (min) t glqv t glqx t avqv data valid
8 ac characteristics write cycle (pre/post-radiation)* -55 c to +125 c for (c) screening and -40 o c to +125 o c for (e) screening (v dd = 5.0v + 10%) notes : * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. functional test performe d with outputs disabled (g high). 2. three-state is defined as 500 mv change from steady-state output voltage (see figure 3). symbol parameter 9q512-25 5.0v min max unit t avav 1 write cycle time 20 ns t etwh chip enable to end of write 20 ns t av e t address setup time for write (e - controlled) 0 ns t av w l address setup time for write (w - controlled) 0 ns t wlwh write pulse width 20 ns t whax address hold time for write (w - controlled) 2 ns t efax address hold time for chip enable (e - controlled) 0 ns t wlqz 2 w - controlled three-state time 10 ns t whqx w - controlled output enable time 4 ns t etef chip enable pulse width (e - controlled) 20 ns t dvwh data setup time 15 ns t whdx data hold time 2 ns t wlef chip enable controlled write pulse width 20 ns t dvef data setup time 15 ns t efdx data hold time 2 ns t av w h address valid to end of write 20 ns t whwl 1 write disable time 5 ns
9 assumptions: 1. g < v il (max). if g > v ih (min) then q(7:0) will be in three-state for the entire cycle. 2. g high for t avav cycle. w t avwl figure 5a. sram write cycle 1: write enable - controlled access a(18:0) q(7:0) e t avav 2 d(7:0) applied data t dvwh t whdx t etwh t wlwh t whax t whqx t wlqz t avwh t whwl
10 t efdx assumptions & notes: 1. g < v il (max). if g > v ih (min) then q(7:0) will be in three-state for the entire cycle. 2. either e scenario above can occur. 3. g high for t avav cycle. a(18:0) figure 5b. sram write cycle 2: chip enable - controlled access w e d(7:0) applied data e q(7:0) t wlqz t etef t wlef t dvef t avav 3 t avet t avet t etef t efax t efax or
11 notes: 1. 50pf including scope prob e and test socket capacitance. 2. measurement of data output o ccurs at the low to high or hi gh to low transition mid-point (i.e., cmos input = v dd /2). 90% figure 6. ac test loads and input waveforms input pulses 10% < 5ns < 5ns v load = 1.55v 300 ohms 50pf cmos 0.5v v dd -0.05v 10%
12 data retention characteris tics (pre-radiation)* (v dd = v dd (min), 1 sec dr pulse) notes: * post-radiation perform ance guaranteed at 25 o c per mil-std-883 method 1019. 1. e1 = v dr all other inputs = v dr or v ss . symbol parameter temp minimum maximum unit v dr v dd for data retention -- 2.5 -- v i ddr 1 data retention current -40 o c -55 o c 25 o c 125 o c -- -- -- -- 10 10 10 45 ma ma ma ma t efr 1 chip enable to data retention time -- 0 -- ns t r 1 operation recovery time -- t avav -- ns v dd data retention mode t r 4.5v 4.5v v dr > 2.5v figure 7. low v dd data retention waveform t efr e
13 packaging 1. all exposed metalized areas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electri cally connected to v ss . 3. lead finishes are in accordance to mil-prf-38535. 4. dimension are in acco rdance with mil-prf-38535. 5. lead position and copl anarity are not measured. 6. id mark symbol is vendor option: no alphanumerics. one or both id methods ma y be used for pin 1 id. 7. letter designators are in accordance with mil-std-1835. 8. dimensions shown are in inches. figure 8. 36-pin ceramic flatpack
14 ordering information 512k x 8 sram: 20 = 20ns access time, 5.0v operation package type: (y) = 36-lead flatpack package (bottom brazed) screening: (notes 3, 4, & 5) (c) = hirel temperature range flow (p) = prototype flow (w) = extended industrial temperature range flow (-40 o c to +125 o c) lead finish: (notes 1 & 2) (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, th en the part marking will match the lead fini sh and will be either ?a? (solder) or ?c? (gold). 3. prototype flow per aeroflex manufact uring flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. hirel temperature range flow per aeroflex manuf acturing flows document. devices are tested at -55 c, room temp, and +125 c. radiation neither tested nor guaranteed. 5. extended industrial temperature range flow per aeroflex manufacturing flows document. devices are tested at -40 c room temp and +125 c. radiation neither tested nor guaranteed. UT9Q512E- * * * * -aeroflex core part number
15 512k x 8 sram: smd 5962 - 00536 lead finish: (notes 1 & 2) (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) case outline: (y) = 36-lead ceramic flatpack (bottom-brazed) class designator: (q) = qml class q (v) = qml class v device type 05 = 20ns access time, 5.0v operation, mil-temp 06 = 20ns access time, 5.0v operation, exte nded industrial temp (-40c to +125c) drawing number: 00536 total dose: ( note 3) (d) = 1e4 (10 krad)(si)) (p) = 3e4 (30 krad)(si)) (l) = 5e4 (50krad(si)) federal stock class designator: no options ** * ** notes: 1.lead finish (a,c, or x) must be specified. 2.if an ?x? is specified when ordering, part marking will match the lead finish and will be eith er ?a? (solder) or ?c? (gold). 3.total dose radiation must be specified when ordering.
16 colorado toll free: 800-645-8862 fax: 719-594-8468 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc., reserves the right to make changes to any products and services herein at any time without notice. consult aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a pr oduct or service from aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. aeroflex colorado springs - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hi-rel
aeroflex colorado springs application note an-mem-002 creation date: 8/19/11 page 1 of 5 modification date: 4/24/13 low power sram read operations * pic = aeroflex?s internal product identification code 1.0 overview the purpose of this application note is to discuss the aeroflex srams low power read architecture and to inform users of the affects associated with the low power read operations. 2.0 low power read architecture the aforementioned aeroflex designed sr ams all employ an archit ecture which reduces power consumption during read accesses. the architecture internally senses data only when new data is requested. a request for new data occurs anytime the chip enable device pin is asserted, or any of the device address inputs transition states while the chip enable is asserted. a trig- ger is generated and sent to the sensing circuit anytime a request for new data is observed. since several triggers could occur simultaneously, these triggers are wire-ored to result in a sing le sense amplifier activity for the read request. this design method results in less power consumption than designs that co ntinually sense data. aeroflex?s low power srams listed above activate the sensing circuit for approximately 5ns whenever and access is reque sted, thereby, signifi cantly reducing active power. table 1: cross reference of applicable products product name: manufacturer part number smd # device type internal pic number:* 4m asynchronous sram ut8r128k32 5962-03236 01 & 02 wc03 4m asynchronous sram ut8r512k8 5962-03235 01 & 02 wc01 16m asynchronous sram ut8cr512k32 5962-04227 01 & 02 mq08 16m asynchronous sram ut8er512k32 5962-06261 05 & 06 wc04/05 4m asynchronous sram ut8q512e 5962-99607 05 & 06 wj02 4m asynchronous sram UT9Q512E 5962-00536 05 & 06 wj01 16m asynchronous sram ut8q512k32e 5962-01533 02 & 03 qs04 16m asynchronous sram ut9q512k32e 5962-01511 02 & 03 qs03 32m asynchronous sram ut8er1m32 5962-10202 01 - 04 qs16/17 64m asynchronous sram ut8er2m32 5962-10203 01 - 04 qs09/10 128m asynchronous sram ut8er4m32 5962-10204 01 - 04 qs11/12 40m asynchronous sram ut8r1m39 5962-10205 01 & 02 qs13 80m asynchronous sram ut8r2m39 5962-10206 01 & 02 qs14 160m asynchronous sram ut8r4m39 5962-10207 01 & 02 qs15
aeroflex colorado springs application note an-mem-002 creation date: 8/19/11 page 2 of 5 modification date: 4/24/13 2.1 the sram read cycles. the data sheets for all the devices noted in table #1 discuss th ree methods for performing a read operation. the two most com- mon methods for reading data are an addr ess access and a chip enabled-controlled access. the third access discussed is the output enable-controlled access. the sequence at which control lines and address inputs are toggled determines which cycle is considered relevant. as discussed in section 2.0, an assertio n of chip enable or any addres s transition while chip enable is asserted, initiates a read cycle. if the de vice chip enable is asserted prior to any address input transitions, then the read a ccess is considered an address access. by keep ing the device enabled and repeatedly switch ing address locations, the user retrieves all data of interest. a chip enable-controlled access occurs wh en the address signals are stable prior to asserting the chip enable. the output enabled-controlled a ccess requires that either an address a ccess or chip enable-controlled access has already been performed and the data is waiting for the output enable pin to assert, driving data to the device i/o pins. the subsequent read cycle verbiage and diagrams are based on the aeroflex ut8r512k8 data sheet. the number of control, input, and i/o pins will vary across the products listed in ta ble 1. the basic design family functionality for read operations is common among all the devices. 2.1.0 address access read cycle the address access is initiated by a change in a ddress inputs while the chip is enabled with g asserted and w deasserted. valid data appears on data outputs dq(7:0) after the specified t avqv is satisfied. outputs remain active throughout the entire cycle. as long as chip enable and output enable are active, the addre ss inputs may change at a rate equal to the minimum read cycle time (t avav ). assumptions: 1. e1 and g < v il (max) and e2 and w > v ih (min) a(18:0) dq(7:0) sram read cycle 1: address access t avav t avqv t axqx previous valid data valid data note: no time references are relevant with respect to ch ip enable(s). chip enable(s) is assumed to be asserted.
aeroflex colorado springs application note an-mem-002 creation date: 8/19/11 page 3 of 5 modification date: 4/24/13 2.1.1 chip enable-controlled read cycle the chip enable-controlled access is initiated by e1 and e2 going active while g remains asserted, w remains deasserted, and the addresses remain stable for the entire cycle. after the specified t etqv is satisfied, the eight-bit word addressed by a(18:0) is accessed and appears at the data outputs dq(7:0). 2.1.1 output enabled-controlled read cycle the output enable-controlled access is initiated by g going active while e1 and e2 are asserted, w is deasserted, and the addresses are stable. read access time is t glqv unless t avqv or t etqv have not been satisfied. 3.0 low power read architecture timing consideration the low power read architecture employed by aeroflex designed srams results in significant power reduction, especially in applications with longer than minimum read cycle times. howeve r, this type of architecture is responsive to excessive input signal skew when device addressi ng and chip enable assertion occur simultaneously. signal skew of greater than 4-5ns between all of the read triggering activities is sufficient to star t another read cycle. assumptions: 1. g < v il (max) and w > v ih (min) a(18:0) sram read cycle 2: chip enable access e1 low or e2 high data valid t efqz t etqv t etqx dq(7:0) note: no specification is given for address set-up time with respect to chip enable assertion. the read cycle description state s that addresses are to remain stable for the entire cycle. address set- up time relative to chip enable is assumed to be 0ns minimum. sram read cycle 3: output enable access a(18:0) dq(7:0) g t ghqz assumptions: 1. e1 < v il (max) , e2 > and w > v ih (min) t glqv t glqx t avqv data valid
aeroflex colorado springs application note an-mem-002 creation date: 8/19/11 page 4 of 5 modification date: 4/24/13 3.1 simultaneous control and address switching simultaneous switching of controls and addr ess pins, alone, is not a problem; excessi ve skew between them is the concern. consider the application where several sr am devices are connected to the same me mory bus. the address bus is commonly connected to all the devices, bu t the chip enable pin is singularly connected to each individual sr am. this configuration results in a loading difference between the address inputs and the chip enable. this li ghtly loaded chip enable propagates to t he memory more quickly than the heavily loaded address lines. th e oscilloscope capture of figure #1 is the actual timing of an application which had intermittent data errors due to address transitions lagging chip enable. figure #1 sram signal capture the signal transitions in the scope plot of figure #1 appear to be fairly coincidental. a closer look however, reveals the chip enable signal actually starts and reaches v il approximately 6ns before the address signal reaches v ih . even at one half v dd (closer to actual logical gate switching of the inputs), the delta in signal times is still approximately 6ns. simultaneous switching of controls and address inputs is not r ecommended for a couple of reasons . the first is the previously described signal skew sensitivity between controls and/or addre ss inputs. the second reason is that activating all the controls and address inputs simultaneously results in peak instantaneous current consumption. this condition causes maximum strain to the power decoupling. chip enable activates address decodi ng circuits, address switching introduces input buffer switching current, and output enable assertion turn s on all the device output drivers. peformi ng all three simultaneously results in wors t case transient current de mand by the memory. 3.1.0 technical overview of skew sensitivity recall from section 2.0 that any activity requesting new data cau ses a read trigger. the trigge rs are wire-ored together. in order to meet the faster access tim es demanded by today?s applica tions, the ored trigger only ex ists during the first 4-5ns of the read cycle. since the slowes t of the address transiti ons occurs more than 5ns after the initiation of the read activity, a sec- ond read activity is initiated. the sensing circuit does not have time to normalize before the second read activity has started . for this reason a chip enable-controlled r ead cycle requires that address inputs rema in stable for the entire cycle. infrequent and random sensing errors can result if th e bit columns are continually pulled to one state then quickly requested to sense the opposite state. another effect of the low po wer read architecture that di ffers from previous generation designs (those that con - tinually sense for data) is that the bit line will not be sensed again until another read triggering event occurs. if another r ead trigger event (chip enable assertion and/or address change) does no occur for a particular addre ss, the incorrect data remains at the outputs. ? timing shown from vil (yellow trace /cs) and vih (pink for address signal) as delta x = 6ns. even at actual internal gate switching point (~ vdd/2), the skew is still around 6ns. chip enable (/e) address signal (ax)
aeroflex colorado springs application note an-mem-002 creation date: 8/19/11 page 5 of 5 modification date: 4/24/13 4.0 summary and conclusion the aeroflex srams in table #1 all employ a low power consum ption read architecture. power is conserved by sensing data only when new data is requested. a request occurs anytime chip enable is asserted or any addr ess input signal transitions while chip enable is asserted. the data sheet s for the srams listed in table #1 do not explicitly define the case of simultaneous switching of address and control signals dur ing read operations. data sh eet read cycle descriptions indicate that control input s are established prior to address changes, and address inputs ar e stable prior to control assertions. simultaneous switching of addresses and controls is tolerable, when the skew between all input signals is < 4ns. for designs that must employ the simul- taneous activation of address and control signals, two important is sues should be considered by the designer. the first is the input signal skew sensitivity of the low power read architectur e discussed by this application no te. the second is the instanta - neous current consumpt ion that results from si multaneous access methods. aeroflex reco mmends the use of only one read access method at a time. if mu ltiple read accesses (simultaneous chip enable assertion and address switching) cannot be avoided, then aeroflex recommends that th e chip enable signal be delayed until all addresses have completed transitions.

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